FIG. 18 shows a conventional memory system. In the drawing, a bus 1802 connected to a memory controller 1801 extends in one direction, and a plurality of memory modules 1804 each mounting thereon a plurality of (two in the drawing) memory chips 1803 are connected in parallel with each other to the bus 1802. In this text, such a connection structure for the bus, i.e., memory interface is referred to as a bus-connection-type interface in a memory device, typically represented by a synchronous DRAM (SDRAM) or a rambus DRAM (RDRAM).
Since the bus-connection-type interface connects a plurality of memory chips or memory modules in parallel with each other to the extending bus, it has a remarkable advantage in connection with the extendibility (increase of the number) of the memories.
However, due to the configuration wherein a plurality of memory chips or a memory modules are connected to the extending bus at respective locations thereof, there arises the problems of a high-level reflection on the transmission line, and a large number of loads (fan-outs) disposed on the transmission line, thereby making it difficult to increase the transmission speed on the bus. It is considered that the transmission speed thereon is limited to around 1 to 2 Gb/s, for example.
In addition, since the memory chips or the memory modules are connected to the extending bus at respective locations, there arise a case wherein the data skew caused by a difference in the length of the transmission line is not negligible. More specifically, the phases of the data input to the memory are different data by data, which prevents the data which should be input simultaneously from being fetched simultaneously, thereby causing a malfunction. This problem appears more significantly along with a higher-speed transmission of the data.
FIG. 19 is a block diagram showing the conventional memory chip. An 8-bit command/address packet, for example, serially fed from the bus is converted into parallel data by a 1:8 demultiplexer (serial-parallel converter circuit), decoded by a packet decoder circuit (decoder) 1902, certified for ID thereof by an ID certification circuit 1903, and then input to a memory core 1904 wherein memory cells are arranged in a matrix.
On the other hand, input data including 8-bit serial data are converted by another 1:8 demultiplexer 1905 into parallel 64-bit data, which are input to the memory core 1904. The output 64-bit data from the memory core 1904 is serially converted by an 8:1 multiplexer 1906, and fed as an 8-bit serial data.
FIG. 20 is a block diagram showing the fetch of the input data in the conventional memory chip, wherein the input data among the conventional input/output data shown in FIG. 19 and the 1:8 demultiplexer are detailed.
If the data width of the input data is 8 bits, for example, then the input data 2001 are fed from a 8-bit bus, and each of data 2001A to 2001H are input to a corresponding one of eight 1:8 demultiplexers 2002A to 2002H. These 8-bit input data 2001A to 2001H are fetched by the 1:8 demultiplexers 2002A to 2002H, respectively, at a single input clock 2004.
A data fetch operation by the conventional memory chip will be described with reference to the timing chart of FIG. 21. The clock 2004 allows the data 2001A to 2001H to be fetched at the same timing, which is substantially the center (shown by dotted line) between a transition of data 2001 to 2001H and another transition thereof.
It is to be noted that the 8-bit input data 2001A to 2001H have some phase deviations therebetween due to a difference in the length of the transmission line along which each data is transferred. These phase deviations are referred to as data skews 2010. If the data skews 2010 are negligibly small compared to the data rate, then the fetch of the 8-bit data at the single clock 2004 can be performed normally.
However, if the data skews are not negligible, i.e., if the transmission speed of the data is higher and does not allow the data skews to be negligible with respect to the data rate, then all the 8-bit data cannot be fetched at the same timing by using a single clock. Thus, one of the limits on the transmission speed of the transmitted data in the conventional memory chip is that a plurality of data having data skews therebetween due to the difference in the length of the transmission line cannot be fetched in the memory chip at the same timing, as described above.
In summary, the first problem in the conventional technique is that since the memory chips or memory modules are connected to the extending bus at the respective locations thereof, a large reflection arises on the transmission line and the loads (fan-out number) on the transmission line increases, whereby it is difficult to raise the transmission speed on the bus.
The second problem in the conventional technique is that since the memory chips or memory modules are connected to the extending bus at the respective locations thereof, the data skews due to the difference in the length of the transmission line is not negligible.
The third problem in the conventional technique is that since there is no effective countermeasure employed against the data skews, there is a possibility that a malfunction may arise.